In the manufacture of semiconductor chips a silicon wafer or other substrate is exposed to a variety of different processes in different processing chambers. The chambers may expose the wafer to plasmas, chemical vapors, metals, laser etching, and various deposition and acid etching processes in order to form circuitry and other structures on the wafer. During these processes, the silicon wafer may be held in place by an electrostatic chuck (ESC). The chuck holds the wafer by generating an electrostatic field to clamp the back side of the wafer to a flat surface or puck surface of the chuck.
As fabrication techniques for plasma processing equipment advance, such as those designed to perform plasma etching of microelectronic devices and the like, the temperature of the wafer during processing becomes more important.
ESCs have been designed for thermal uniformity across the surface of the substrate, sometimes called a workpiece. ESCs use liquid cooling to absorb the plasma power heat and remove it from the chuck. An ESC may also include independently controlled heaters in multiple zones. This allows for a wider process window under different process and plasma conditions. Individual heater zones in the radial direction can create various radial temperature profiles which compensate for other etch process radial non-uniformities. However, radial heaters cannot affect non-uniformities in the azimuthal direction.
In semi-conductor etch processing, the temperature of a wafer during processing influences the rate at which structures on the wafer are etched. Other processes may also have a temperature dependence. This temperature influence is present, for example, in conductor etch applications in which very precise wafer temperature control helps to obtain a uniform etch rate. A more precise thermal performance allows for more precisely formed structures on the wafer. Uniform etch rates across the wafer allow smaller structures to be formed on the wafer. Thermal performance or temperature control is therefore a factor in reducing the size of transistors and other structures on a silicon chip.